Browse Prior Art Database

Program Logic Array With Metal Level Personalization

IP.com Disclosure Number: IPCOM000087240D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Balasubramanian, PS: AUTHOR [+2]

Abstract

A program logic array is made up of read-only storage cells interconnected to generate a desired logic function. This disclosure describes a technique for stockpiling a standard array of masterslice read-only storage cells which can be personalized on the metal level to provide a program logic array having the desired complex logic function. The utilization of segmented diffusions coupled with two levels of metallization combine to eliminate the parasitic capacitance normally found in an array.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Program Logic Array With Metal Level Personalization

A program logic array is made up of read-only storage cells interconnected to generate a desired logic function. This disclosure describes a technique for stockpiling a standard array of masterslice read-only storage cells which can be personalized on the metal level to provide a program logic array having the desired complex logic function. The utilization of segmented diffusions coupled with two levels of metallization combine to eliminate the parasitic capacitance normally found in an array.

The array structure of a typical field-effect transistor (FET) memory array or programmable logic array has long diffusions which are used for source and drain connections, which create parasitic capacitances. The capacitances create large RC time constants in the array to slow signal propagation from input to output.

Previous usage of two levels of metallization in arrays to minimize this RC time constant have not been effective in reducing the diffusion capacitances associated with the long source and drain diffusion rails.

The technique disclosed herein reduces both the diffusion resistance and a large portion of the diffusion capacitance to enable the rapid propagation of signals along the array from input to output. As shown, the amount of capacitance remaining is directly proportional to the umber of gates present along any source/drain diffusion row.

This layout makes use of the concept of diffusion stitching which requires no unique diffusion lev...