Browse Prior Art Database

Modified Weinberger Image for Enhanced Wirability of LSI Chips

IP.com Disclosure Number: IPCOM000087241D
Original Publication Date: 1976-Nov-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Love, RD: AUTHOR

Abstract

This modified Weinberger image permits enhanced wirability of large-scale integration (LSI) chips.

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Modified Weinberger Image for Enhanced Wirability of LSI Chips

This modified Weinberger image permits enhanced wirability of large-scale integration (LSI) chips.

The figure illustrates how an improved field-effect transistor (FET) layout configuration for either enhancement or enhance/deplete FET device technologies can be implemented. In the prior Weinberger image, the spaced diffusion array is perpendicular to the power bus structure and to most of the intercircuit connect wiring. The disadvantages inherent in the Weinberger layout are that all cross column wiring contains substantial diffusion runs which have a high capacitance and are resistive and, furthermore, for wide columns the circuit connections to the drain and ground potentials are via diffusions, which have a relatively high resistance and decrease the circuit performance for increasing column width.

The circuit layout shown in the figure has the source and drain diffusions parallel to the drain and ground potential bus structure.

All load devices can be connected to the drain potential bus at a vertical location where the extended metal output will pass directly over the gate with that signal as its input and directly over the circuit output diffusions which drive that output. Specifically, in the figure, load device FET 1 has an associated output via contact A.

The metal wiring goes directly over the circuit output contact F and directly to the FET 9 which it is driving. Each circuit ground diffus...