Browse Prior Art Database

Address Channel Trap

IP.com Disclosure Number: IPCOM000087251D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 73K

Publishing Venue

IBM

Related People

Goodheart, RJ: AUTHOR [+2]

Abstract

The address channel trap (ACT) of Fig. 1 is a combined software and hardware service tool, in a separate enclosure, designed to monitor data busses, registers, and selected lines within a user's system, such as the IBM System/7. It significantly reduces the time needed by development programmers and field systems engineers in debugging their programs, and also reduces the time required to isolate design problems and hardware malfunctions by development engineers and field engineers. The data flow of the ACT is illustrated in Fig. 2. Up to 32 events of 18 bits each may be stored in storage 2 and displayed by the use of external syncing and operator controls. Additional control signals are provided to interface the user's system, e.g., Stop to System on line 4 and Stop on Condition on line 5 from the system.

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Address Channel Trap

The address channel trap (ACT) of Fig. 1 is a combined software and hardware service tool, in a separate enclosure, designed to monitor data busses, registers, and selected lines within a user's system, such as the IBM System/7. It significantly reduces the time needed by development programmers and field systems engineers in debugging their programs, and also reduces the time required to isolate design problems and hardware malfunctions by development engineers and field engineers. The data flow of the ACT is illustrated in Fig. 2. Up to 32 events of 18 bits each may be stored in storage 2 and displayed by the use of external syncing and operator controls. Additional control signals are provided to interface the user's system, e.g., Stop to System on line 4 and Stop on Condition on line 5 from the system.

The performance specifications are significant as the ACT can trap signals at a rate of 16.6 megawords/second. This is accomplished by freezing data already on bus 1 being monitored at the time of the external sync pulse on line 6. Data present on bus 1, 10 nanoseconds prior to the leading edge of the sync, is stored in storage 2.

One noteworthy feature is the method of storing the data being monitored. The Write to Storage line 9 is held active normally. This allows writing into the first storage location constantly. The data being monitored may change any time. However, when the leading transition of the user's sync pulse is sensed, Write to Storage is inhibited. This allows the data present on the input lines to be frozen at the leading edge of the sync pulse. During the time that Write to Storage is inhibited, the internal storage address register is incremented, allowing new data to be written into the next storage location.

In the basic operation of the ACT, two states or conditions are important, Reset and Stop. In the Reset state and in run mode, ACT is activated and waiting for an external sync pulse on lines 7 and 8.

The Write to Storage line 9 is active until the leading edge of the sync pulse...