Browse Prior Art Database

Asynchronous Interface Controls

IP.com Disclosure Number: IPCOM000087256D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Nagel, DM: AUTHOR

Abstract

Passing data from one processor, such as an IBM System/7, to another via a group of digital input (DI) and digital output (DO) lines requires a strobe signal to tell the receiving processor that data is present and an acknowledge (DO ACK) signal to tell the sending processor that data has been received. Conventional interconnection of the DO strobe bit directly to the receiver process interrupt (PI) circuit input requires alternation of the receiver circuit reference register to look first for a rise of the sender circuit strobe bit and next for a fall. This software manipulation adds significantly to the time required for processing in each system, and hence reduces the potential data rate.

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Asynchronous Interface Controls

Passing data from one processor, such as an IBM System/7, to another via a group of digital input (DI) and digital output (DO) lines requires a strobe signal to tell the receiving processor that data is present and an acknowledge (DO ACK) signal to tell the sending processor that data has been received. Conventional interconnection of the DO strobe bit directly to the receiver process interrupt (PI) circuit input requires alternation of the receiver circuit reference register to look first for a rise of the sender circuit strobe bit and next for a fall. This software manipulation adds significantly to the time required for processing in each system, and hence reduces the potential data rate.

The circuit illustrated in Figs. 1 and 2 interconnects the DO strobe bit, the DO ACK bit and the PI bit of each system in a manner that permits a higher data rate. If system A of Fig. 1 is the sender, applying a strobe signal to the DO line 3 conditions the exclusive OR (OE) circuit 5 to apply an output signal to the PI line 2 of each system. This is seen as an interrupt at System B. System B acknowledges reception by applying an ACK signal to its DO line 3. With signals at both inputs of circuit 5, its output signal is removed from PI line 2. This condition interrupts System A and the cycle is complete with a monodirectional change of the PI signal effecting an interrupt at each system each cycle.

Fig. 2 shows the system interconnection in mor...