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NRZI Receive and Decode Circuit

IP.com Disclosure Number: IPCOM000087266D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Porter, DD: AUTHOR

Abstract

This circuit is a hardware implementation of an architectural requirement which enables modems utilizing internal clocking to maintain synchronization.

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NRZI Receive and Decode Circuit

This circuit is a hardware implementation of an architectural requirement which enables modems utilizing internal clocking to maintain synchronization.

Referring to Fig. 1, NRZI (non-return-to-zero change on ones recording) data coding requires that for any binary zero value being sent over a teleprocessing link the value of the transmitted data must change from its previous state. This change in the data requires the receiver to decode the NRZI value back to its proper logical value. The NRZI function can be performed in software at either the controller level or the CPU level. This approach implements the NRZI function at the hardware level.

The hardware implementation of the NRZI receive and decode circuit operates as follows:
Last Value Received Present Value Received Actual (NRZ) Value 1 1 1

0 1 0

1 0 0

0 0 1.

The operation which is performed by the NRZI receive and decode circuit is to compare (exclusive NOR function) the last value received with the present value received. The circuit in Fig. 2 is one implementation of the NRZI receive and decode circuit, as used in conjunction with the IBM Synchronous Data Link Control Communications attachment.

The last value received is remembered by the latch L comprising blocks 1, 2 and 3. Once the comparison is made and the received data is stored in the shift register (SR), the Clock (CLK) 2 pulse resets the latch and the present received value becomes the last (remembered) value for t...