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"On Line" Error and Statistics Logging in Large Data Base Systems

IP.com Disclosure Number: IPCOM000087268D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 41K

Publishing Venue

IBM

Related People

Heimsoth, AJ: AUTHOR [+2]

Abstract

The system significantly reduces central processing unit (CPU) overhead and/or "data resources busy" during error or statistical logging and analysis, by adding a high speed buffer roughly twice the size of an existing logging processor's main storage and modifying or adding to the logging processor's microcode, a module which, intercepts the input/ output (I/O) processor's log requests, processes them to the buffer and logs them to a log device on an as-required basis.

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"On Line" Error and Statistics Logging in Large Data Base Systems

The system significantly reduces central processing unit (CPU) overhead and/or "data resources busy" during error or statistical logging and analysis, by adding a high speed buffer roughly twice the size of an existing logging processor's main storage and modifying or adding to the logging processor's microcode, a module which, intercepts the input/ output (I/O) processor's log requests, processes them to the buffer and logs them to a log device on an as- required basis.

Typically, in large data base systems, such as illustrated above, the CPU 1 does not directly control the detailed sequences required to GET and PUT data. Normally, the CPU passes parameters to an I/O processor 2 or service processor, which in turn accesses the I/O devices 3. This allows the CPU to perform other operations while waiting for the data. Data is passed to and from the CPU by means of a direct memory access or a cycle stealing I/O channel.

Within the I/O processor or service processor subchannel, there must be some means of detecting device errors and, in some large systems, the recording of statistical data logs pertaining to usage and changes of data modules, etc. Normally routines are provided in the I/O processor code (microcode), to handle, log and recover from errors during on-line operations.

In illustrating typical large systems architecture with respect to logging errors and statistics, the figure shows only one direct memory access (DMA) channel 4 and one I/O processor 2 for simplicity. Typically, I/O processor 2 contains the necessary microprograms to control the normal accessing and transferring of data between the data resource and main CPU storage.

Difficulties arise when hardware errors or usage counter overflows plague the throughput performance of the system. During this situation the I/O processor 2 requests a log sequence to the logging processor 6. This sequence is initiated in an effort to keep error recovery off-line to CPU 1.

When acknowledged by logging processor 6, the I/O processor 2 passes the raw error or statistical information to logging processor 6 for analysis and recording. Normally the recording device selected is an inexpensive, relatively low speed virtual device 7 (e.g., floppy disk).

The processing of the raw data by logging processor 6 may be quite lengthy depending on the number of accesses required to the log device and the amount of analysis to be performed. In some cases transients of program modules, required to analyze the data, may also be resident on the log device.

During the time this logging is in process I/O processor 2 may be waiting to initiate another log request. If this situation exists, I/O processor 2 must now return BUSY to subsequent I/O GET-PUT commands from CPU 1. The end result is reduced system throughput and increased "data resource busy" situations. Difficulties are compounded in system configurations where the

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