Browse Prior Art Database

Pacing System for ROS Controlled Machines

IP.com Disclosure Number: IPCOM000087269D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Pitt, GA: AUTHOR [+2]

Abstract

Paging is an addressing technique commonly used to expand the directly addressable storage area of a system. The system described is primarily directed to processors whose instructions are normally executed from a read-only storage (ROS), but the technique can also be effectively applied to those systems having their instructions in a random-access memory.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 60% of the total text.

Page 1 of 2

Pacing System for ROS Controlled Machines

Paging is an addressing technique commonly used to expand the directly addressable storage area of a system. The system described is primarily directed to processors whose instructions are normally executed from a read- only storage (ROS), but the technique can also be effectively applied to those systems having their instructions in a random-access memory.

When programs are contained in a ROS, some mechanism must be used to communicate and/or to convey status and control information between pages. Conventionally, this has been accomplished via a stack of working registers but this limits the amount of information which can be communicated at a reasonable expense. A combination of random-access memory and ROS, configured as shown in the drawing, will greatly expand the range of such communications at only a small cost of time and hardware.

In the figure, there are a number of pages 1 of ROS, each having storage addresses of 0 to Y and being selectable by the processor using the ROS. A single section of random-access memory 2 is associated with all of the ROS pages and contains the storage addresses Y + 1 to X. The processor is assumed to be capable of addressing X storage locations by direct address so that the random-access memory is always accessed by a direct address and is not dependent upon the page select controls for the ROS.

It is evident that the block of random-access memory is logically contained within each of...