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Power Minimization of LSSD SRLS

IP.com Disclosure Number: IPCOM000087309D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Flaker, RC: AUTHOR [+2]

Abstract

This article discloses a technique for minimizing power in shift register latch networks (SRLS). In today's design of large-scale integrated circuit networks, the amount of power used becomes critical and can require expensive forced air cooling, causing the unit to be economically infeasible. Since testing is also a problem with such large networks, a design known as level sensing scan design (LSSD) is employed which permits the designer to have tests generated automatically for his network. One of the basic building blocks of this design discipline is the shift register latch. These shift register latches, as shown in Fig. 1, comprise two latches in each stage. Latches 1A and 1B are serially coupled to the logic arrays and are the only latches used during system operation.

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Power Minimization of LSSD SRLS

This article discloses a technique for minimizing power in shift register latch networks (SRLS). In today's design of large-scale integrated circuit networks, the amount of power used becomes critical and can require expensive forced air cooling, causing the unit to be economically infeasible. Since testing is also a problem with such large networks, a design known as level sensing scan design (LSSD) is employed which permits the designer to have tests generated automatically for his network. One of the basic building blocks of this design discipline is the shift register latch. These shift register latches, as shown in Fig. 1, comprise two latches in each stage. Latches 1A and 1B are serially coupled to the logic arrays and are the only latches used during system operation. Thus the parallel latches 2A and 2B are not needed for functional operation, but are needed during testing. However, in previous designs the latches 2A and 2B were constantly powered up even during functional operation.

It has been determined that by coupling each of the second latches 2A and 2B to a pulse power circuit, significant power can be saved by depowering each of the parallel latches 2A and 2B during functional operation and permitting the powering of the parallel latches 2A and 2B only during testing operation of the entire network.

Fig. 2 depicts a typical latch L2 and its associated pulse power circuit. As shown, the latch comprises two parallel cu...