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Browse Prior Art Database

Bipolar Logic Level to FET Logic Level Buffer Circuit

IP.com Disclosure Number: IPCOM000087310D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Lewis, SC: AUTHOR [+3]

Abstract

In many integrated circuit applications, field-effect transistor (FET) logic and memory circuits are required to accept low level bipolar input logic signals, such as those provided by transistor-transistor logic (TTL) or emitter-coupled logic (ECL). This buffer circuit provides the necessary level conversion with increased speed using a minimum of timing signals.

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Bipolar Logic Level to FET Logic Level Buffer Circuit

In many integrated circuit applications, field-effect transistor (FET) logic and memory circuits are required to accept low level bipolar input logic signals, such as those provided by transistor-transistor logic (TTL) or emitter-coupled logic (ECL). This buffer circuit provides the necessary level conversion with increased speed using a minimum of timing signals.

The buffer circuit operates as follows: during a nonactive portion of the operating cycle of the buffer, that is, prior to t0 restore, pulse R is high, turning on precharge devices T1 and T2 to precharge the gates of bootstrap output drivers T3 and T4. At the same time, since phase 1 is at zero volts and control voltage VT is greater than the threshold voltage of T8, node 4 is also at zero volts, keeping isolation devices T5 and T6 off. Restore pulse R is also applied to gating devices T7 and T9, allowing reference voltage Vref and logic input signal Vin to be coupled to nodes 2 and 3, respectively. The cross-coupled pair T10 and T11 are maintained in an unlatched condition since latch set device T12 is off. Vin may switch logic levels any time prior to t0. At t0 there is a slight delay in order to allow Vin to precharge node 3. At t1 time restore pulse R is brought to ground, isolating the signals on nodes 2 and 3.

At t2 time, phase 1 rises and causes three things to occur. First, phase one is coupled through voltage boosting capacitors C1 and C2 to independently couple the isolated signals on nodes 2 and 3 to higher voltages, increasing the dri...