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Decoupling Capacitor Placement

IP.com Disclosure Number: IPCOM000087359D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Parisi, J: AUTHOR

Abstract

On semiconductor chips with large delta currents (delta I), it is desirable to put decoupling capacitors in close proximity to the semiconductor chip pads. The closer the capacitor leads are to the chip pads, the smaller the lead parasitic inductance. This reduction of inductance maximizes the effectiveness of any decoupling capacitor.

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Decoupling Capacitor Placement

On semiconductor chips with large delta currents (delta I), it is desirable to put decoupling capacitors in close proximity to the semiconductor chip pads. The closer the capacitor leads are to the chip pads, the smaller the lead parasitic inductance. This reduction of inductance maximizes the effectiveness of any decoupling capacitor.

To achieve this result, the decoupling capacitor is mounted on the backside of each integrated circuit chip. This provides the most effective application of all the capacitance at the highest frequency to the integrated circuits. Via holes may be formed through the chip at wafer level by etching holes or laser drilling.

The figures show three possible configurations. Fig. 1 shows etched via holes 4 through the semiconductor chip 5. The decoupling capacitor 6 is mounted on the backside of the chip 5 by any suitable technique, such as solder bonds 7. The chip is in turn mounted to a substrate 8 face down by solder bonds
9. The conductor 10 connects the capacitor 6 to the frontside of the chip 5. Figs. 2 and 3 show arrangements similar to Fig. 1, where like numbers indicate like structures. The difference in Fig. 2 is that the holes are laser-milled, and the conductor 10 completely fills the holes. The difference in Fig. 3 is that the conductor 10 is formed around the edge of the chip rather than through holes.

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