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Dynamic Random Access Memory

IP.com Disclosure Number: IPCOM000087367D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Ho, IT: AUTHOR [+2]

Abstract

This is a bipolar dynamic random-access memory cell.

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Dynamic Random Access Memory

This is a bipolar dynamic random-access memory cell.

The bipolar memory cell illustrated in the drawings is characterized by high density and relatively fast access time because the read operation takes place through a path with a relatively low RC time constant. As shown in Fig. 1, only two lines (one word line and one digit line) are required to access a desired cell. Each cell consists of a PNP transistor T1 and an NPN transistor T2. In order to access cell 10, for example, a signal on word line 1 and a signal on digit line 1 will provide access to the cell.

As illustrated in the top view of Fig. 2a and the cross-sectional view of Fig. 2b, all cells in the same column share the same N type region forming the base of the PNP transistor and the collector of the NPN transistor. The digit lines are formed by the buried N+ subcollector regions. Each cell has two metal contacts, one to the emitter of the PNP transistor, the other to the emitter of the NPN transistor. This arrangement assures the prevention of parasitic SCR effects within the cell. A single metal line which is the word line contacting both transistors at the emitter is required.

The operation of this memory cell is illustrated by the pair of wave-form diagrams in Fig. 3. When writing a "1", the word line is brought to an up level and the digit line is brought to a down level, rendering the PNP transistor T1 conductive. With a properly designed word line driver circuit, the floating base region of the NPN transistor T2, which is also the collector of the conducting PNP transistor, will assume a high pot...