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FIFO Clocked Data Rate Buffer

IP.com Disclosure Number: IPCOM000087368D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Ross, BM: AUTHOR

Abstract

A first-in, first-out (FIFO)-clocked buffer storage register is disclosed for shifting an M bit-wide word at twice the clock rate into the first available word register in a sequence of word shift registers. Race conditions between successive word shift registers in the register sequence is avoided by strobing the odd-numbered registers together at times when the even-numbered registers are not strobed and vice versa.

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FIFO Clocked Data Rate Buffer

A first-in, first-out (FIFO)-clocked buffer storage register is disclosed for shifting an M bit-wide word at twice the clock rate into the first available word register in a sequence of word shift registers. Race conditions between successive word shift registers in the register sequence is avoided by strobing the odd-numbered registers together at times when the even-numbered registers are not strobed and vice versa.

The seven NOR (or NAND) circuits 1-7 of Fig. 1 comprise a control circuit 8 for shift register 9, storing the first M bit-wide word. There is no limit to the value of M except that which is caused by the drive capability of the strobe signal on line 10. There also is no limitation on the number of word shift registers, like register 9, that can be connected in sequence.

Clock signals C1 and C2 are connected in like manner to the alternate word register control circuits, e.g., control circuits 8 and 11. Clock signals C1 and C2 are connected in inverted manner to the intervening alternate control circuits, e.g., control circuits 12 and 13. Consequently, the even-numbered words stored in registers 14 and 16 are strobed together, and the odd-numbered words stored in registers 9 and 15 are strobed together. The result is that although data only enters the overall data rate buffer (at word register 9) upon each occurrence of a C1 clock signal, the data propagates through the buffer from word register to succeeding word register at twice th...