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Parallel Cyclic Redundancy Check Using Programmable Logic Array

IP.com Disclosure Number: IPCOM000087370D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Ross, BM: AUTHOR

Abstract

A cyclic redundancy check (CRC) on input data requires a translation of the input data and of old CRC accumulator data into new CRC accumulator data. Such translation is simply defined in the case of a single data bit. For a byte of input data, the translation is accomplished efficiently using a PLA (programmable logic array) personalized so that it will respond to an initial (old) accumulator value of Most Significant Bits (MSB) Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Value A B C D E F G H I J K L M N P Q and four bits of input data MSB Bit 0 1 2 3 Value R S T U. to produce new accumulator bit values determined in accordance with the expressions given below: (Image Omitted)

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Parallel Cyclic Redundancy Check Using Programmable Logic Array

A cyclic redundancy check (CRC) on input data requires a translation of the input data and of old CRC accumulator data into new CRC accumulator data. Such translation is simply defined in the case of a single data bit. For a byte of input data, the translation is accomplished efficiently using a PLA (programmable logic array) personalized so that it will respond to an initial (old) accumulator value of Most Significant Bits (MSB)

Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Value A B C D E F G H I J K L M N P Q and four bits of input data MSB

Bit 0 1 2 3

Value R S T U. to produce new accumulator bit values determined in accordance with the expressions given below:

(Image Omitted)

The above expressions are derived from the polynomial X/16/ + X/12/ + X/5/ + 1.

The circuit configuration for carrying out the four-bit CRC algorithm is represented in Fig. . Four bits 0-3 (D(1)) of an eight bit data bus (D(1)+ D(2)) and the remaining four bits 4-7 (D(2)) are loaded into buffer latches B(1) and B(2), respectively, upon the occurrence of clock C(1). After B(1) is loaded from D(1), C(3) is activated to load a new accumulator value, as defined by the above equations, using the four data bits of B(1) and the previous (feedback) CRC accumulator value. C(2) is then activated to move the four data bits of B(2) into B(1). Clock C(3) is then activated again to compute the new accumulator value derived from the new data...