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Browse Prior Art Database

Hierarchy Memory for Improved Microprocessor Performance

IP.com Disclosure Number: IPCOM000087371D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR [+2]

Abstract

The cost/performance of microprocessors is enhanced by using an on-chip hierarchy of registers/buffers and arrays for general-purpose register space. Microprocessor performance enhancement is achieved through faster access to selected programs that protect regions or boundaries using an on-chip hierarchy of registers and storage.

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Hierarchy Memory for Improved Microprocessor Performance

The cost/performance of microprocessors is enhanced by using an on-chip hierarchy of registers/buffers and arrays for general-purpose register space. Microprocessor performance enhancement is achieved through faster access to selected programs that protect regions or boundaries using an on-chip hierarchy of registers and storage.

Fig. 1 shows a "page store" chip hierarchy for memory protection regions. The contents of the selected program is transferred from the main storage 4 to registers RO through RN 6 in one storage cycle. The registers can be direct map or set associated buffers. The register access 8 and cycle is much faster than the storage access and cycle. Since the protection region is now available at a faster data rate from registers, the overall microprocessor performance is enhanced.

Fig. 2 shows a register space with on-chip active pages. Microprocessor performance enhancement is achieved through faster access to the active pages of general register space for a selected program. Prior to program execution, the selected pages of register space are transferred into the high-speed portion of the chip, i.e., register/ retained in the array structure 16.

Fig. 3 shows an "intermix memory". Microprocessor cost/performance enhancement is achieved by balancing the performance characteristics of two or more storage units with the programming mix of the microprocessor and its application. In other words...