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# Error Detecting Correcting System

IP.com Disclosure Number: IPCOM000087376D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 53K

IBM

## Related People

Challande, JF: AUTHOR

## Abstract

There are proposed new structures for detecting and correcting multiple errors in the transmission of data bits, which are used iteratively at both emission and reception sides and thus enable a saving in logic function design to be obtained.

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Error Detecting Correcting System

There are proposed new structures for detecting and correcting multiple errors in the transmission of data bits, which are used iteratively at both emission and reception sides and thus enable a saving in logic function design to be obtained.

The new structure is based on square transformation matrixes having two properties. First, they are orthogonal, i.e., for any square matrix M, the transformed matrix T(M) is such that in each row or column there is only one element of the original row or column of matrix M. Secondly there is a number N such that the N/th iterative transformation is the identity transformation T/N/(M) =
M. Certain of these transformation matrixes have the additional property of exchanging rows and columns.

Data bits are divided in sequences of n2 bits which can be arranged according to matrixes M (n x n). These sequences are iteratively transformed into T(M), T/2(M),......T/N-1(M) by a transformation unit. From each transformed
matrix, sets of parity bits P(M), P(T) P(T)2....... are generated by a parity-bit
generator (one parity bit by row, for instance). The sets of generated parity bits are all emitted, but only the transformed matrix T /N-1/(M) is transmitted.

Upon reception, the matrix T/N-1/(M) is iteratively transformed into T/N/(M) =
(M), T/2/(M).........T/N-2/(M) by a transformation unit identical to the one of the
transmitter. Likewise, from each transformed matrix, sets of parity bits P(T)n-1, P(M), P...