Browse Prior Art Database

Inverse Mesa Etch Power Device Process

IP.com Disclosure Number: IPCOM000087388D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Laff, RA: AUTHOR [+2]

Abstract

The following process steps simplify power transistor manufacture by allowing the backside metallization to serve both as the chip package metallurgy and as the mesa etch mash to define chip geometry. Referring to the figure, the steps are as follows:

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Inverse Mesa Etch Power Device Process

The following process steps simplify power transistor manufacture by allowing the backside metallization to serve both as the chip package metallurgy and as the mesa etch mash to define chip geometry. Referring to the figure, the steps are as follows:

1) Photolithograph and etch the frontside SiO(2), diffuse boron to obtain the P type base region 12 in the N- type substrate 10, and reoxidize SiO(2)layer 14 on the frontside.

2) Photolithograph and etch the front emitter opening and backside collector opening, diffuse the emitter 16 and collector 18 regions, and reoxidize SiO(2).

3) Photolithograph the front contact hole areas and etch SiO(2).

4) Deposit Al-Cu emitter contact 20 and base contacts 22, and subtractive etch to remove metal from all other areas.

5) Photolithograph and etch the collector contact hole areas.

6) Electroless plate Ni-Au collector contacts 24. Ni-Au will not deposit over the SiO(2).

7) Sinter Al-Cu and Ni-Au.

8) Remove SiO(2) 26 from the backside.

9) Mesa etch Si from the backside through the entire chip. The Ni-Au areas will act as a self-aligned etch mask.

10) Attach the chip to the package at the collector contact with Pb-Sn preform, attach the base and emitter leads, and passivate the chip.

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