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Isolation for Individual High Voltage Testing of Mesa Transistors at the Wafer Level

IP.com Disclosure Number: IPCOM000087389D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Perner, FA: AUTHOR [+2]

Abstract

In mesa processing of transistors, no isolation exists between the base regions of individual transistors. Hence, if one transistor on a wafer containing more than 100 transistors has poor high-voltage characteristics, it will affect the measurement of the high-voltage parameters of all the transistors on the wafer. Because of this, it has been a practice to dice and package all the transistors on the wafer before the high voltage parameters are screened. The packaging costs of the bad transistors then must be absorbed in the cost of the good transistors. If bad transistors could be eliminated at the wafer level, the overall packaging cost would be reduced.

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Isolation for Individual High Voltage Testing of Mesa Transistors at the Wafer Level

In mesa processing of transistors, no isolation exists between the base regions of individual transistors. Hence, if one transistor on a wafer containing more than 100 transistors has poor high-voltage characteristics, it will affect the measurement of the high-voltage parameters of all the transistors on the wafer. Because of this, it has been a practice to dice and package all the transistors on the wafer before the high voltage parameters are screened. The packaging costs of the bad transistors then must be absorbed in the cost of the good transistors. If bad transistors could be eliminated at the wafer level, the overall packaging cost would be reduced.

A process modification is described here to introduce isolation between mesa high-voltage transistors to allow high-voltage testing at the wafer level. The base diffusion is done through a special base diffusion mask, so that it is possible to isolate each transistor, allowing the high-voltage characterization of the transistors at the wafer level. Bad transistors can be marked and eliminated before packaging.

The isolation is provided by masking areas about the periphery of the individual transistors before the base diffusion. Furthermore, the isolation areas can have medial stripe-like diffusions which combine to form conventional guard rings (as in planar high-voltage transistors) to control the curvature breakdown voltage...