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High Frequency Analog Electronic Delay Using Phase Locked Loop Techniques

IP.com Disclosure Number: IPCOM000087405D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

McCarthy, WF: AUTHOR [+2]

Abstract

The circuit provides a programmable electronic delay with 100% usable range, ease of alignment and excellent linearity and drift characteristics.

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High Frequency Analog Electronic Delay Using Phase Locked Loop Techniques

The circuit provides a programmable electronic delay with 100% usable range, ease of alignment and excellent linearity and drift characteristics.

The conventional means for providing a voltage-controlled programmable delay of a timing pulse for use in test systems utilizes an analog ramp generator and voltage threshold comparator. When a ramp is initiated, the control voltage is used to vary the threshold at which the ramp triggers an output and, thereby, positions the output as a function of that voltage. Such a circuit requires the use of many discrete parts in generating an accurate ramp, has difficulty in achieving a linear ramp, and has the inability to program the delay over the full cycle of input frequency.

The present arrangement makes use of a phase-locked-loop (PLL) to position the phase of an oscillator signal relative to the input trigger frequency. Fig. 1 shows a basic PLL 10 where feedback 12 causes the voltage-controlled oscillator (VCO) to speed up or slow down, maintaining close to zero phase relationship with the input reference signal 16. The high gain amplifier 18 in the loop makes that phase error very small.

The introduction of a control voltage 20 (Fig. 2) to the summing point 22 of the amplifier 18 causes the output phase of the VCO 14 to shift relative to the input such that the output voltage of the phase detector 24 exactly cancels the control voltage applied. Th...