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Overflow Indication in Two's Complement Arithmetic

IP.com Disclosure Number: IPCOM000087407D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

East, DG: AUTHOR [+2]

Abstract

In an adder performing two's complement arithmetic, the arithmetic overflow indication is often generated by exclusive-ORing the carry into the high-order bit position with the carry out of the high-order bit position. However, when such an adder is constructed using integrated circuit adder modules (each containing, for example, four bit positions of the total adder), the carry into the high-order bit position is not available, and the overflow indication cannot be generated in the usual manner.

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Overflow Indication in Two's Complement Arithmetic

In an adder performing two's complement arithmetic, the arithmetic overflow indication is often generated by exclusive-ORing the carry into the high-order bit position with the carry out of the high-order bit position. However, when such an adder is constructed using integrated circuit adder modules (each containing, for example, four bit positions of the total adder), the carry into the high-order bit position is not available, and the overflow indication cannot be generated in the usual manner.

In the following truth table, CI is the carry input to the high order bit position of the adder; A and B are the high-order addenda and augend bits; CO is the carry out of the high-order bit position; S is the high-order sum bit; and 0 is the overflow indication (that is, the exclusive-OR of CI and CO). CI A B CO S 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 0 1 1 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 1 0 .

Inspection of the truth table will show that 0 can be determined when A, B and S are known. There will be an overflow when each of A and B is the inverse of S. The above figure shows three examples of circuits which will generate the overflow indication as a function of A, B and S. Each of the circuits uses simple AND (A), OR (0), EXCLUSIVE-OR (XOR) and INVERT (I) logic blocks.

The above logic circuits, and any of their equivalents, can also be used for overflow generation in circumstances where an arithmetic mo...