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Incrementing Decrementing Add Unit

IP.com Disclosure Number: IPCOM000087428D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Bodner, RE: AUTHOR [+3]

Abstract

A computer system may have a storage address of 2N bits and an arithmetic and logic unit (ALU) of N bits. If the ALU is assigned to do address incrementing, decrementing and indexing, it would be necessary to either take two passes through the ALU or expand it to 2N bits. Neither of these alternatives may be appropriate under certain speed constraints. The solution to meet speed and cost objectives is to provide an incrementing and decrementing N-bit add unit (AU) in addition to the ALU. The carry from the ALU is entered into the AU, but to minimize the logic, the decrement function is exclusively ORed with the ALU carry out. Further, since the output of the AU is gated, the AU result logic is designed to incorporate the gating logic and thereby minimize the logic for the two functions.

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Incrementing Decrementing Add Unit

A computer system may have a storage address of 2N bits and an arithmetic and logic unit (ALU) of N bits. If the ALU is assigned to do address incrementing, decrementing and indexing, it would be necessary to either take two passes through the ALU or expand it to 2N bits. Neither of these alternatives may be appropriate under certain speed constraints. The solution to meet speed and cost objectives is to provide an incrementing and decrementing N-bit add unit (AU) in addition to the ALU. The carry from the ALU is entered into the AU, but to minimize the logic, the decrement function is exclusively ORed with the ALU carry out. Further, since the output of the AU is gated, the AU result logic is designed to incorporate the gating logic and thereby minimize the logic for the two functions. This results in both speed and cost advantages.

Fig. 1 is a partial showing of a computer system having an addressable main storage 10 (N-bits wide) which is addressed by an address (2N bits) in main storage address register (MSAR) 11. MSAR 11 is loaded at the appropriate time with the contents (2N bits) of a selected local storage register (LSR) 30. The contents of the selected LSR 30 are also applied to XH REG 40 and XL REG 50 for incrementing or decrementing by ADD UNIT (AU) 100 and ALU 200. The incremented or decremented address is returned to the selected LSR 30 via ALU GATE 70 and LSR GATE 80. Hence, the entire address is incremented or decremented in one operation.

One-byte operand arithmetic/logical operations are performed using ALU 200 without the use of AU 100. One operand from a selected LSR (low) 30, for example, is set into the Y REG 60 and another operand from storage 10, for example, is set into XL REG 50. The result can be returned to storage 10.

Two-byte operands (two storage fetches are required and thus there is no time degradation) involve both the use of ALU 200 and AU 100. During a first cycle, the contents of a selected LSR 30 are set into XH REG 40 and XL REG 50. The low byte of the two-byte operand is fetched from storage 10 and set into Y REG 60. The contents of XL REG 50 and Y REG 60 are operated upon by ALU 200 and the result is returned to the selected LSR 30 via ALU GATE 70 and LSR GATE 80.

On the next cycle, the contents of XH...