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Optical Cross Level Register Addressing

IP.com Disclosure Number: IPCOM000087429D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Eggebrecht, LC: AUTHOR

Abstract

In many processors a set of general purpose registers are associated with each interrupt level. This reduces the status saving and restoring time when interrupt levels are switched. Many times it is necessary for a program on one level to inspect or write the registers of another level. This would require an instruction including an OP code, an encoded level value and a register address. It will be appreciated that such a mode of operation requires an extra OP code decode for each type of register operation. Also, an additional instruction field is required to identify the level of the register to be accessed.

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Optical Cross Level Register Addressing

In many processors a set of general purpose registers are associated with each interrupt level. This reduces the status saving and restoring time when interrupt levels are switched. Many times it is necessary for a program on one level to inspect or write the registers of another level. This would require an instruction including an OP code, an encoded level value and a register address. It will be appreciated that such a mode of operation requires an extra OP code decode for each type of register operation. Also, an additional instruction field is required to identify the level of the register to be accessed.

If the system supports indirect register operations, the above mentioned facilities can be added without the need for extra OP codes or instruction fields.

In most systems the register "indirected from" has a width in bits much greater than the address field of the register array, thus the information needed to implement the above-mentioned facility can be packed into the unused bits of the register.

For example, consider the instruction, "Write Accumulator to Register Indirectly" in a device using a 16-bit or two-byte word. With one byte of the register indirected from specifying the OP code and the other the register to be loaded, such other byte will typically contain a number of unused bits. If four bits are used to designate the register, four bits remain unused and may be utilized to specify a level. Using two o...