Browse Prior Art Database

Virtual Local Storage Registers

IP.com Disclosure Number: IPCOM000087430D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Check, GP: AUTHOR [+3]

Abstract

In computer systems (Fig. 1) having input/output controllers (IOCs) 30 attached to control a plurality of input/output devices (I/O) 40 or teleprocessing lines, it is possible to use work registers of the IOC as local storage registers (LSRs) for the central processing unit (CPU) 15. Normally each I/O device 40 or teleprocessing line would require its own LSR in the CPU 15 to provide addresses for addressing storage 10 during transfer of data between it and storage 10.

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Virtual Local Storage Registers

In computer systems (Fig. 1) having input/output controllers (IOCs) 30 attached to control a plurality of input/output devices (I/O) 40 or teleprocessing lines, it is possible to use work registers of the IOC as local storage registers (LSRs) for the central processing unit (CPU) 15. Normally each I/O device 40 or teleprocessing line would require its own LSR in the CPU 15 to provide addresses for addressing storage 10 during transfer of data between it and storage 10.

Data field addresses furnished to IOC 30 (Fig. 2) are stored in IOC registers
32. A single I/O LSR 16 in CPU 15 is dedicated for use by IOC 30. When storage 10 is to be addressed, the address in a selected LSR, i.e., LSR 16, is transferred into storage address register (SAR) 17. If data is being written into storage 10, it must reside in storage data register (SDR) 18 at the time storage 10 is being addressed. Register 18 can be loaded from Data Bus In (DBI) 25 via A register 20 and arithmetic and logic unit (ALU) 21. When data is read from storage 10, it enters SDR 18 and becomes available on Data Bus Out (DBO) 26.

In order to use the single I/O LSR 16 as an address source for each of the I/O devices 40 attached to controller 30, it is necessary to provide data to A register 20 and a control signal to ALU 21 for modifying the address in LSR 16.

Prior to the time that data is to be transferred between IOC 40 and storage 10, IOC 30 determines which I/O device 40 or teleprocessing line is involved in the data transfer. IOC 30 then takes a present address from register 31 and a data field address from one of the registers 32, i.e., the one associated with the involved I/O device 40, and computes an address modify factor for modifying the high and low bytes of the address in LSR 16. The computed modify factor is stored in register 33 along with the correct sign to signify addition or subtraction of the modify factor.

The data field address in register 32 then becomes the present address and is loaded into...