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RAS Loading

IP.com Disclosure Number: IPCOM000087432D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Dumstorff, EF: AUTHOR [+3]

Abstract

Random-access storage (RAS) is loaded by a microcontroller having address registers for at least two program levels by using a minimum of additional logic. The address register associated with the inactive program level contains the RAS address where data is to be written. An instruction associated with the active level causes the operation to switch to the inactive program; however, before the change takes place a write instruction, which had been fetched during the execution of the instruction for effecting the switching, is executed. The write instruction execution is extended and the data furnished to RAS is written therein at the address contained in the formerly inactive level address register. The write signal also causes an interrupt which returns the operation to the active level.

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RAS Loading

Random-access storage (RAS) is loaded by a microcontroller having address registers for at least two program levels by using a minimum of additional logic. The address register associated with the inactive program level contains the RAS address where data is to be written. An instruction associated with the active level causes the operation to switch to the inactive program; however, before the change takes place a write instruction, which had been fetched during the execution of the instruction for effecting the switching, is executed. The write instruction execution is extended and the data furnished to RAS is written therein at the address contained in the formerly inactive level address register. The write signal also causes an interrupt which returns the operation to the active level.

Only the pertinent logic is shown in Fig. 1; other elements normally included in a microcontroller are not shown. Register 13 is supplied with addresses for the active program level, i.e., it is supplied with an address which will address the read only storage (ROS) 5. The instruction from ROS 5 is sent on bus 15 to the microcontroller for execution in the usual manner. One of the instructions taken from ROS 5 will cause a RAS address to be loaded in register 12. The microinstruction taken from ROS 5, which is being executed at point A (Fig. 2) is a Control Immediate Write (KIW) instruction. Execution of this instruction causes the interrupt to be reset in the microcontroller which in turn causes selector 14 to select register 12 as the address source. The selection of the new address source takes place at point D (Fig. 2). Execution, however, of an I/O Write (IOW) instruction has already been started at point C. The IOW instruction was fetched starting at point B during the execution of the KIW instruction.

A program level change cannot take place at point C because execution of the IOW instruction from the current program level is overlapped with the access of the first instruction from the new level. RAS LOAD latch 20 is set under microprogram control. This latch provides an input to AND circuit 21 which also receives an IOW signal on line 31, a clock 7 signal on line 32, and signals from inverters 30 and 35. AND circuit 21 controls the setting of an I/O EXTEND latch 2...