Browse Prior Art Database

TP Line Jitter Trap

IP.com Disclosure Number: IPCOM000087434D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 88K

Publishing Venue

IBM

Related People

Cook, KA: AUTHOR [+2]

Abstract

Serial data transmitted over a teleprocessing (TP) line is monitored and recorded at the same time as the data processing system is receiving the data including actual errors as they occur.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 68% of the total text.

Page 1 of 3

TP Line Jitter Trap

Serial data transmitted over a teleprocessing (TP) line is monitored and recorded at the same time as the data processing system is receiving the data including actual errors as they occur.

In Fig. 1 the serial data coming over line 10 enters modem 11 in the usual manner. The data then passes via an electronics industry adapter (EIA) 12 to the systems communication adapter 15. The significant details of adapter 15 are shown in Fig. 2. Four signal lines (received data from modem (R DATA), internal receive timing (internal clock), receive timing from modem (RCV TIMING) and the byte sync pulse (FLAG/SYN DET)) within adapter 15 are monitored by a systems control adapter (SCA) 60 Fig. 1. Monitoring is selective by the communications I/O controller (IOC) 50, which is a microprocessor including microcode for generating a Select Monitor signal. The Select Monitor signal is applied to gate 16 (Fig. 2) in adapter 15 to control passage of the four signals mentioned above on lines 17, 18, 19 and 20.

The gated signals are passed to SCA 60 via common card 30. Bus 21 leaves gate 16 and connects to inverter 31 in common card 30 (Fig. 3) to provide inputs via funnel logic (gating) 32 and bus drive circuitry 33 to SCA bus (8 bits)
61.

Common card 30 also receives data in byte form from adapter 15 over data bus in (DBI) 22. This data is then passed to IOC 50 for transmission to processor 80. Data errors are detected by IOC 50, and upon detection of an error, the...