Browse Prior Art Database

Slave Clock Synchronization

IP.com Disclosure Number: IPCOM000087445D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Enser, MM: AUTHOR

Abstract

A method is described for synchronizing a slave clock to several master clocks within a fixed priority arrangement.

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Slave Clock Synchronization

A method is described for synchronizing a slave clock to several master clocks within a fixed priority arrangement.

In Fig. 1, the purpose of the unit A is to keep its output Q at the same frequency as input I(1) as long as I(1) is a valid signal. If I(1) falls out of phase, the unit A should switch to I(2) as a reference, but keep its output Q in the same phase as before. While the unit A is synchronized on I(2) it must monitor I(1) for validity, and when found valid, Unit A should switch back from I(2) to I(1).

In Fig. 2, a number of master clock inputs (I(1) - I(N)) are connected to a master clock selector having an output to a phase detector. The phase detector is connected to a processor unit which controls the phase and frequency of a slave clock.

If a controlling master clock input falls out of phase, which will be detected by the phase detector, a control word from read-only storage (ROS) in the processor will initiate a down routine in an up/down controller so that the master clock selector will switch the master clock control from the actual input to the next lower priority input.

However, when the phase detector detects a valid input for the next higher priority master clock input, an up routine will be initiated in the up/down controller.

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