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Machine Supported Branch Table Within Interrupt Classes

IP.com Disclosure Number: IPCOM000087453D
Original Publication Date: 1977-Jan-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Attanasio, CR: AUTHOR

Abstract

A current lack in computing systems is the ability to support a high transaction rate in an environment requiring interactive access to a large shared data base. Measurements on current systems indicate that the limiting factor in many cases is the speed of the central processing unit, and that a substantial percentage of the instructions executed are in the control program. This technique is directed toward reducing the number of instructions a control program must execute during interruption processing, specifically, those instructions by which the control program selects its main processing routine on the basis of the detailed information accompanying the interruption.

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Machine Supported Branch Table Within Interrupt Classes

A current lack in computing systems is the ability to support a high transaction rate in an environment requiring interactive access to a large shared data base. Measurements on current systems indicate that the limiting factor in many cases is the speed of the central processing unit, and that a substantial percentage of the instructions executed are in the control program. This technique is directed toward reducing the number of instructions a control program must execute during interruption processing, specifically, those instructions by which the control program selects its main processing routine on the basis of the detailed information accompanying the interruption.

In the IBM System/37O, there are five classes of interruptions to the central processing unit (CPU), some generated internally within the CPU, others by other elements of the system, such as input/output sub-system, various timers, etc. When the CPU accepts an interruption, a new "program status word" for the class is loaded, which includes the address of the next instruction to be executed. Additionally, an "old" program status word and an interruption code are stored, specifying, respectively, the state of the CPU before the interruption and some detailed information which varies with the class of the interruption. For example, the class of "program interruption" is divided into 21 subclasses by the interruption code.

For each of the five classes of interruption, the main storage locations for new and old PSWs and interruption code are distinct.

As a consequence, sometimes substantial numbers of instructions are executed by control programs to decode the information associated with the interruption before the actual processing of the interruption begins. For example, for program interruptions, the software control program must discover whether the program interruption was due to a translation exception, invalid instruction, etc., before entering the appropriate routine to process the condition, even though this information was available in the hardware when the interruption was presented.

It is proposed herein that an associative set of hardware registers be defined for each class of interruption (not necessarily the same number for each class, and the number may be zero). These registers can be loaded under program control. Each entry contains an interruption code within the class, an instruction address to be entered directly upon occurrence of an interruption of that class and that interruption code, (i.e., overriding the instruction addre...