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DC Card Test With Dynamic Latches

IP.com Disclosure Number: IPCOM000087461D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 99K

Publishing Venue

IBM

Related People

Peck, RH: AUTHOR

Abstract

Apparatus is described for testing logic containing dynamic latches using a DC Multi-Purpose Test System Tester.

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DC Card Test With Dynamic Latches

Apparatus is described for testing logic containing dynamic latches using a DC Multi-Purpose Test System Tester.

The symbols used in the circuit blocks are:

A = And N = Inverter (Not)

FF = Flip-flop OE = Exclusive OR

ZR = Resistor block Reg = 4-bit shift register

C = Capacitor Z = Impedance network

L = Inductance Y = Crystal

TIEDN = Tie down (Ground)

In Fig. 1, phase outputs PH1 and PH2 must have a fixed relationship to one another. PH2 must rise 400 ns after the fall of PH1, otherwise the capacitive storage in the dynamic latches may dissipate. If PH2 rises too soon or overlaps PH1, then logic signals may flush through several logic levels and cause errors. The unmodified tester can change one logic input line every 32 us. This means that the time from the fall of PH1 to the rise of PH2 is 32 us.

One approach is to provide a detector on an associated tester program board that causes a change of events, which results in a pulse on PH2 line after the fall of PH1. The implementation uses one shot modules. When PH2 is told to change by the program, the program board ignores the command because it has already generated the pulse. The logic on the cards is so structured that both PH1 and PH2 may be forced high simultaneously in order for the tester to "dot and" with PH1 and PH2.

A number of changes may be introduced to provide a more effective method. One change is the creation of an oscillator in digital logic because the "cut" program deletes the analog oscillator. A second change is to generate a circuit which will both logically and physically generate the required pulses on the PH2 line. Third, embellishments are introduced which will allow the tester to emulate a processor, such as the IBM Word Processor/32 unit, and utilize associated Magnetic Card diagnostics to check the card in the tester. Fourth, the oscillator on the card under test is used for the test and is not wired off the card and jumpered back onto the card at the system level, as previously required.

This particular system requires a pulse 1200 ns wide or wider on PH1, followed, after a 400 ns delay time, by a PH2 clock which is 1200 ns long or longer. PH2 may not overlap PH1 and a dead (both clocks at zero) time of 400 ns has been chosen to separate PH2 and PH1. For this purpose, a 2.5 MHZ (1/400 ns) oscillator was chosen which was divided into eight equal parts, three parts for PH1, one part for clock separation, three parts for PH2 and one part for normal separation between PH2 and PH1.

The oscillator may be degated from the logic by test point MTPO4 (Fig. 2). When the oscillator has been degated, then single clock pulses may be inserted by means of MTP02. These two tests are required to prove that the logic can...