Browse Prior Art Database

Microprocessor with Additional Random Access Memory

IP.com Disclosure Number: IPCOM000087466D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Dixon, JD: AUTHOR

Abstract

The structure described in this article will provide an additional area of random-access memory in a microprocessor by the use of a paging scheme which does not require the programmer to know when paging occurs.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

Microprocessor with Additional Random Access Memory

The structure described in this article will provide an additional area of random-access memory in a microprocessor by the use of a paging scheme which does not require the programmer to know when paging occurs.

A particular small microprocessor can address directly up to 4k bytes of storage, usually read-only storage (ROS) but possibly random-access memory, and this will usually be reserved for the operating program. The storage area can be increased by a method called paging to provide space for additional instructions and for data. This storage will normally be random-access memory, and individual 4k-byte sections will be called into action by paging instructions and then addressed by the same addresses as are used for the ROS so the programmer must be aware of the storage page being used.

The present structure enables the use of some paging that is transparent to the program and provides additional random-access memory for data. In the above diagram, the basic 4k storage is in blocks 1, 2, 3 and 4 of 1k bytes each and can be either ROS or random-access memory. A block will be selected by the two high-order bits of a storage address which will energize one of the quadrant lines 5, 6, 7 or 8. The remaining address bits will go to all storages 1, 2, 3 and 4 to select an individual storage address in the activated block. Additional storage for data can be supplied by providing one or more blocks 9 of random-access memory, and this a...