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Instruction Fetch Execution Overlap Method for a Microprocessor Used as a Microcontroller

IP.com Disclosure Number: IPCOM000087468D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Dixon, JD: AUTHOR

Abstract

This system includes a microprocessor that is used mostly as an Input/Output (I/O) controller and that is preferably run as fast as possible with given technology. A fetch/execution overlap technique is described that allows storage cycles to be used at maximum efficiency for the fetching and execution of instructions.

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Instruction Fetch Execution Overlap Method for a Microprocessor Used as a Microcontroller

This system includes a microprocessor that is used mostly as an Input/Output (I/O) controller and that is preferably run as fast as possible with given technology. A fetch/execution overlap technique is described that allows storage cycles to be used at maximum efficiency for the fetching and execution of instructions.

The system includes a host central processing unit (CPU) 1 with an associated channel 1a, storage 2, and a device attachment 3 incorporating a microcontroller 4 for the interconnection of a CRT display unit 5 having a keyboard 6 and display screen 9. A device card 7 ( Fig. 2) mounts various circuit chips as follows: C = Channel

M = Microprocessor

CRT = Cathode Ray Tube

ROS = Read-Only Storage

Random-Access Memory.

Fig. 3 shows the microcontroller data flow and system components. I/O data coming into the microcontroller goes to the Register Stack 11 and I/0 data leaving comes from Stack 11. The contents of two registers, both from the Stack 11 only or one from Data Address Register (DAR) Stack 13 and one from Stack 11 may be sent through the Arithmetic Logic Unit (ALU) 12 and the results placed in either Stack 11 or DAR Stack 13. The ALU functions are ADD, SUB, AND, OR, and XOR. In addition, Move and Test functions may be performed.

Data from Storage 15, addressed by DAR Stack 13 or absolute from the instruction, may be placed in the Stack 11 or if read-write storage is used, data from the Stack 11 may be written in storage. All data storage operations use two nibbles (4 bits each) so that full bytes are handled.

Instructions, as addressed by the Instruction Address Register (IAR) 16 are placed in the Operation (Op) register 17. All instructions are 16 bits wide. A Branch address may originate from the immediate data in the instruction or from the DAR Stack 13 or from the Link registers.

The microcontroller starts after a Controller Reset, or Power On, by fetching the first instruction of the "day". This first cycle is the only one during which no instruction execution takes place. From that cycle on, the microcontroller is one instruction ahead, and while executing the present instruction, it will be fetching the next instruction. This I/E overlap makes efficient use of every storage cycle such that the storage cycle time becomes the instruction cycle time.

There are two types of instructions that take two cycles each since they reference Storage 15 themselves. They are the "Load" and "Store" to memory instructions. Since these instructions must take two cycles to complete and it is desired not to waste storage cycles, one of the two cycles is overlapped between the next instruction fetch and the handling of data associated with the instruction.

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Each two-cycle instruction will be discussed separately. First, and the simplest, is the "Load" instruction. The Load instruction is used to load one byte of data from Sto...