Browse Prior Art Database

Loading Microcode From a Processor to a Microcontroller

IP.com Disclosure Number: IPCOM000087471D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 75K

Publishing Venue

IBM

Related People

Brown, LW: AUTHOR [+2]

Abstract

Under certain circumstances, before read only storage (ROS) modules can be installed in input/output (I/O) cards using a microcontroller, the microcode must be checked out using random-access memory modules. This is a method to load the microcode into the random-access memory modules so they can simulate ROS modules.

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Loading Microcode From a Processor to a Microcontroller

Under certain circumstances, before read only storage (ROS) modules can be installed in input/output (I/O) cards using a microcontroller, the microcode must be checked out using random-access memory modules. This is a method to load the microcode into the random-access memory modules so they can simulate ROS modules.

The system in Fig. 1 includes a host central processing unit (CPU) 1 with associated channel 1a, storage 2, and a device attachment 3 incorporating a microcontroller 4 for interconnection of a CRT display unit 5 having a keyboard 6 and display screen 9. A device card 7 (Fig. 2) mounts various circuit chips as follows: C = Channel

M = Microprocessor

CRT = Cathode Ray Tube

ROS = Read Only Storage

Random-Access Memory.

The microcode for the microcontroller M used on the I/O attachment card 7, shown in Fig. 2, is contained in the ROS modules, such as modules 10, but before the ROS modules can be manufactured, the microcode must be debugged. This is done by using random-access memory modules, such as modules 11. These may be integral with, or separate from, card 7.

Referring to Fig. 3, in order to load the microcontroller microcode from the processor system into the random-access memory modules on the I/O attachment cards, the initial program load (IPL) latch 1 and the reset latch 2 are set by a Set IPL signal on line 3. This places the micro-controller and the processor interface attachment logic in the IPL state.

A processor system Write command is now issued, and byte theta of the System Data Bus 4 is loaded with the System Data Strobe 5 into the data register 6 and the data is placed on the microcontroller Data Bus In (DBI) bits theta-7.

At the same time, the start clock latch 8 is set by the System Data Strobe 5. The setting of the start clock latch 8 does two things. It resets reset latch 2, and causes the microcontro...