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Ordering Component Diagnosis and Improving the Efficiency of Backtrace Procedure

IP.com Disclosure Number: IPCOM000087500D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 5 page(s) / 63K

Publishing Venue

IBM

Related People

Narasimha, MS: AUTHOR [+2]

Abstract

Introduction. Electronic package assemblies, such as modules and cards, are generally manufactured by assembling replaceable components on appropriate carriers (cards or module substrates) which provide the interconnections between components through buried or discrete wiring. Such assemblies are tested to detect defective components and defects introduced during the assembly process. The tests applied are structure-oriented and are normally generated based on the hardware structure using an automatic test generator. Proving diagnosis for a product failing such tests is an essential sequel to testing. This constitutes identifying the defects causing the failure to initiate an appropriate repair action.

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Ordering Component Diagnosis and Improving the Efficiency of Backtrace Procedure

Introduction. Electronic package assemblies, such as modules and cards, are generally manufactured by assembling replaceable components on appropriate carriers (cards or module substrates) which provide the interconnections between components through buried or discrete wiring. Such assemblies are tested to detect defective components and defects introduced during the assembly process. The tests applied are structure-oriented and are normally generated based on the hardware structure using an automatic test generator. Proving diagnosis for a product failing such tests is an essential sequel to testing. This constitutes identifying the defects causing the failure to initiate an appropriate repair action.

Two common ways of performing diagnosis are: (1) using the results of fault simulation, and (2) on-line probing using backtrace procedure.
I. Diagnosis by Using Results of Fault Simulation

Fault simulation is normally performed assuming single stuck-at-0 or stuck-at-1 type faults in the logic circuit gates. The purpose of fault simulation is to identify all the single stuck faults which cause the response at each observable output to be different from its expected response in the absence of the assumed fault. This information is used to compute the diagnostics based on the observed failing response of the product. For any given failing response, many faults may be identified since several stuck faults may have the same fault signature. The resolution of these faults to the components that contain them forms the diagnosis. Such diagnosis points to many components depending on the design and the level of integration, since each test can detect many faults. Replacing all of these components is not desirable because of the high cost of components involved. Furthermore, a purely physical defect at an intercomponent net may not always be corrected by such component replacement. Ideally, it is desirable to have to replace only the defective component(s) or to rectify the defective net(s).
II. On-Line Probing Using Backtrace Procedure

The objective here is to probe the nets along the failure propagation path in order to determine the `terminal net' which is defined as: (a) the defective net in the case of a net defect causing the test failure, or (b) a failing output net of a component with all its input nets not failing, in the case of a defective component causing the test failure. The necessary steps are outlined below.

Step 1 Select any failing observable output or net. Regard this as a preterminal net.

Step 2 Identify the component driving this net. (See the comment under Step 1 of the

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"Diagnostic Ordering of Components".)

Step 3 Form a candidate net list with all the relevant input nets to the component.

Step 4 Probe the nets in the candidate net list in any order until either (a) a failing net is established - in this case, the preterminal...