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Source Destination Failure Detection for a Common Bus

IP.com Disclosure Number: IPCOM000087501D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Britt, RF: AUTHOR [+2]

Abstract

Many processor designs include common buses, over which data or control information may be transmitted from a number of different sources to a number of different destinations. Gate control circuits switch information to and from the bus as required by control words. The information transmitted over the bus is normally parity-checked, which allows detection of failures in the transmission of information bits, but which normally cannot detect failures in gate control circuits. Good parity is maintained if the wrong source is gated onto the bus, or if the information is inadvertently gated into an incorrect destination. The present arrangement allows the normal parity-check mechanism to detect a high percentage of gate malfunctions.

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Source Destination Failure Detection for a Common Bus

Many processor designs include common buses, over which data or control information may be transmitted from a number of different sources to a number of different destinations. Gate control circuits switch information to and from the bus as required by control words. The information transmitted over the bus is normally parity-checked, which allows detection of failures in the transmission of information bits, but which normally cannot detect failures in gate control circuits. Good parity is maintained if the wrong source is gated onto the bus, or if the information is inadvertently gated into an incorrect destination. The present arrangement allows the normal parity-check mechanism to detect a high percentage of gate malfunctions.

The drawing shows a typical arrangement of source registers 3 and 5, destination registers 7 and 9, and one register 11, which can act as either a source or destination.

As shown, source information from the control word is fed to a source code generator 13, and destination information is fed to a destination code generator
15. The source code is routed to all destinations over a source code bus 17, and directed to decoders 19. A destination code bus 21 carries the destination code to encoders 23 at all sources. Each destination is also equipped with a unique destination decoder 25, while each source is equipped with a unique source encoder 27.

At each source, the encoder pair 23, 27...