Browse Prior Art Database

Tie Up Tie Down Mechanism for Input Pins on LSI Chips

IP.com Disclosure Number: IPCOM000087504D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Hester, RL: AUTHOR [+2]

Abstract

A tie-up/tie-down mechanism is described for connecting selected input pins for combinational logic circuits on large-scale integration (LSI) chips to fixed "on" and "off" voltage levels. This is accomplished without using for this purpose any of the module input pins for the module in which the LSI chips are packaged. This mechanism can be used to implement different logical functions on LSI chips having the same circuit layout.

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Tie Up Tie Down Mechanism for Input Pins on LSI Chips

A tie-up/tie-down mechanism is described for connecting selected input pins for combinational logic circuits on large-scale integration (LSI) chips to fixed "on" and "off" voltage levels. This is accomplished without using for this purpose any of the module input pins for the module in which the LSI chips are packaged. This mechanism can be used to implement different logical functions on LSI chips having the same circuit layout.

A representative embodiment is shown in the drawing in a highly simplified manner. It is assumed that three LSI integrated circuit chips 10, 11 and 12 are packaged in a single LSI module 13. Typically, these chips are mounted on one or more substrates located within the module package. Typically, each chip will have somewhere on the order of 600 to 700 circuits formed thereon. In order to emphasize an important application of the tie-up/tie-down mechanism, it is assumed that two of these chips, namely, chips 10 and 11, are of identical construction, that is, that the circuits and circuit connection patterns formed on each of chips 10 and 11 are identical. Thus, chip 10 includes an AND circuit 14 and an OR circuit 15, while chip 11 includes an AND circuit 16 and an OR circuit
17. The third chip, chip 12, is assumed to be of a different construction but, for simplicity, is shown as including an AND circuit 18 and an OR circuit 19. This showing of an AND circuit and an OR circuit on each chip is intended as a simplified representation of the several hundred logic circuits on each chip.

The tie-up/tie-down mechanism makes use of some of the scan only scan ring latches which are normally fabricated on the chips for other purposes, namely, for establishing various initial starting conditions for the machine in which the chips are used. Typically, several scan only scan ring latches are formed on each of the LSI chips. These latches are connected to one another in a serial manner to form a scan latch string. Representative ones of these scan ring latches are indicated at 20 and 21 on chips 10 and 11, respectively. During the initial setup or loading of the machine, these latches are set to the desired conditions by scanning in the appropriate setup values in a serial manner. This is accomplished by way of a scan-in line 22 and a shift line 23. The setup values are placed on the scan-in line 22 one at a time and then shifted in from one latch stage to the next by way of shift pulses on the shift line 23 until the entire string of scan ring latches is loaded up with the proper starting condition values.

The tie-up/tie-down mechanism is implemented by dedicating certain ones of these scan ring latches to provide the tie-up/tie-down function. Typically, one of the several scan ring latches on each chip is dedicated to this purpose. Thus, the latch 20 is dedicated to this purpose on chip 10 and the latch 21 is dedicated to this purpose on chip 11. In the case...