Browse Prior Art Database

Injection Logic Gate

IP.com Disclosure Number: IPCOM000087523D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Chin, WB: AUTHOR [+2]

Abstract

This gate circuit provides high density and performance coupled with low power dissipation.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Injection Logic Gate

This gate circuit provides high density and performance coupled with low power dissipation.

The circuit in Fig. 1 performs the NAND function in which the outputs are at the down level if all inputs are at the up level. The circuit requires low-voltage- drop Schottky barrier diodes (SBD) at the output to reduce logic swings and increase speed proportionately.

As shown in Figs. 2 and 2A, the circuit structure in the chip is rectangular, with T1 and T2 being isolated from each other. The usual injection logic gates, on the other hand, integrate the transistors into a common bed.

To prevent T2 from saturating, thereby improving switching speed, a parasitic resistor may be incorporated between the base of T2 and ground. As shown, this requires no additional silicon area.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]