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Fabricating Ion Implanted Regions in Semiconductors

IP.com Disclosure Number: IPCOM000087543D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 107K

Publishing Venue

IBM

Related People

Doulin, J: AUTHOR [+4]

Abstract

This process provides a more uniform insulator thickness over the base and collector regions of integrated circuit transistors during fabrication, thereby minimizing undercutting and providing adequate junction passivation.

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Fabricating Ion Implanted Regions in Semiconductors

This process provides a more uniform insulator thickness over the base and collector regions of integrated circuit transistors during fabrication, thereby minimizing undercutting and providing adequate junction passivation.

Fig. 1 illustrates a partially completed transistor structure formed in a semiconductor wafer according to a standard process. An insulating layer 5 of silicon dioxide is disposed over collector region 2, whereas no oxide is disposed over base region 4. Oxide layer 5 over region 2 is then stripped prior to the base reoxidation step illustrated in Fig. 2. The reoxidation step then results in a smaller thickness differential between oxides 9 and 7 grown over base region 4 and collector region 2, respectively. The reason for the differential is that silicon dioxide tends to grow faster over N regions than over P regions. Without the stripping process, the silicon dioxide thickness differential would have been much greater.

The process continues with the standard deposition (not shown) of silicon nitride 10 and silicon dioxide followed by the etching of the silicon nitride over all of the contact regions. The exposed portions of the silicon dioxide layers 7 and 9, among others, below the nitride layer are then removed by a dip-etching process. No masks are required. Because oxide region 7 over collector 2 is only around 400 angstroms thicker than oxide region 9 over base 4, problems of undercutti...