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T/2/L Exclusive OR

IP.com Disclosure Number: IPCOM000087555D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Montegari, F: AUTHOR

Abstract

The exclusive OR circuit depicted in the drawing includes three transistor-transistor logic (T/2/L) AND invert circuits.

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T/2/L Exclusive OR

The exclusive OR circuit depicted in the drawing includes three transistor- transistor logic (T/2/L) AND invert circuits.

The exclusive OR function is performed in circuits 1 and 2 by interconnecting the emitter of T4 with the emitter of T10, and the emitter of T6 with the emitter of T5. The collectors of circuits 1 and 2 are dotted and connected to node E of circuit 3, which subsequently provides inversion and full fanout of ten drive capability at node G.

Inputs C and D may be used to obtain exclusive OR AND functions. Inputs F provide AND inhibit of node G.

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