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Five Transistor Shift Register Cell

IP.com Disclosure Number: IPCOM000087558D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Debord, P: AUTHOR [+2]

Abstract

This shift-register cell is an improvement over the seven-transistor shift-register cell described in the IBM Technical Disclosure Bulletin, Vol. 16, No. 10, March 1974, p. 3261-3262. The improvement basically consists in the suppression of the inverter T(1) and associated load T(2). This cell allows a pseudo-static operation in the cell area of a dynamic one with a 30% reduction in power consumption. Also, it provides dynamic operation when it is used only as a shift cell with 30% less area than the well-known cell of six devices.

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Five Transistor Shift Register Cell

This shift-register cell is an improvement over the seven-transistor shift- register cell described in the IBM Technical Disclosure Bulletin, Vol. 16, No. 10, March 1974, p. 3261-3262. The improvement basically consists in the suppression of the inverter T(1) and associated load T(2). This cell allows a pseudo-static operation in the cell area of a dynamic one with a 30% reduction in power consumption. Also, it provides dynamic operation when it is used only as a shift cell with 30% less area than the well-known cell of six devices.

This five-transistor cell, as well as the prior seven-transistor cell, requires two nonoverlapping basic clocks phi1 and phi2 and two signals A and B derived from phi1. Also, A or B is connected to phi1. When A is connected to phi1, B is then connected to ground, and vice versa.

However, to assure the correct polarity of the output signals, the train of B pulses must be an even number. This limitation results from the above- mentioned suppression of an inverter circuit. Referring to the figure, the following elements are identified: T(1) - T(2) = transfer devices T(4) = load device to precharge node F T(3) = inverter T(5) = recirculating gate CA, CD = pull-up capacitance C(13) = intermediate storage capacitance CC = storage capacitance.

A. Shift operation. A is tied to phi1, and B is tied to GROUND. During phi2, nodes C and F are precharged to phi2 - V(T4)(V(T4) = V threshold T(4)). Next during phi1, node C remains up or goes down to zero depending upon data stored in the previous stage. a. Assume node C remains up (logic one). During phi1, CB is charged and node D reaches phi1 - V(T1). Next during phi2, a part of the charge of node D is transferred to node E in the ratio of C(B) and C(C). This ratio must be chosen in order that the voltage reached by node E becomes greater than V(T3)(CC<CB). When phi2 goes down, T(3) remains on and discharges node F. The next stage will receive a zero. b. Assume node C is down (logic ze...