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Improvement to Integrated Injection Logic

IP.com Disclosure Number: IPCOM000087567D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Gillett, JB: AUTHOR

Abstract

Fig. 1 shows an example of an integrated injection logic (I/2/L) circuit. A constant current source (+) forces current I through the circuit, and the Inputs either sink this current or permit it to turn on the output transistors. Typically, such a circuit requires less than one volt between the (+) and (-) busses of the supply. One way to provide the current source is to use a standard 5 volt regulated supply and a series resistor, but this is highly dissipative.

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Improvement to Integrated Injection Logic

Fig. 1 shows an example of an integrated injection logic (I/2/L) circuit. A constant current source (+) forces current I through the circuit, and the Inputs either sink this current or permit it to turn on the output transistors. Typically, such a circuit requires less than one volt between the (+) and (-) busses of the supply. One way to provide the current source is to use a standard 5 volt regulated supply and a series resistor, but this is highly dissipative.

If, however, logic chips of the same current requirement are series- connected, as in Fig. 2, the regulated current I can be provided from a source 10 in an accurate and yet nondissipative manner. To enable this, a family of circuits are provided on the chips to accommodate the input and output levels to the series connection.

These circuits are defined as follows: Upside Driver 12 - Circuit driving an input on a chip at a more negative voltage in the supply chain. Upside Receiver 14 - Circuit receiving an input from a chip at a more negative voltage in the supply chain. Downside Driver 16 - Circuit driving an input on a chip at a more positive voltage. Downside Receiver 18 - Circuit receiving an input from a chip at a more positive voltage. Intermediate Translator 20 - Circuit providing voltage translation between nonadjacent chips in supply chain.

Fig. 3 shows the basic upside, downside relationship of 12, 14, 16 and 18, and Fig. 4 shows the inclusion of interm...