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MOSFET Devices to Determine Mask Alignments Electrically

IP.com Disclosure Number: IPCOM000087588D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 6 page(s) / 161K

Publishing Venue

IBM

Related People

Beilstein, KE: AUTHOR [+2]

Abstract

Special device designs are presented to determine alignments between various masking steps involved in metal-oxide semiconductor field-effect transistor (MOSFET) fabrication using electrical techniques which can be routinely utilized. A structure is also presented which can determine alignment between ion-implantation level and gate/contact level on a wafer which, using conventional methods, is almost impossible to accomplish.

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MOSFET Devices to Determine Mask Alignments Electrically

Special device designs are presented to determine alignments between various masking steps involved in metal-oxide semiconductor field-effect transistor (MOSFET) fabrication using electrical techniques which can be routinely utilized. A structure is also presented which can determine alignment between ion-implantation level and gate/contact level on a wafer which, using conventional methods, is almost impossible to accomplish.

Fabrication of MOSFET structures requires various masking steps which have to be aligned to each other accurately. For example, in metal gate technologies, the first mask ("A" level) is used to open diffusion windows followed by diffusion, drive-in and oxide regrowth. The second mask ("B" level) then is aligned to the shapes on the wafer to open contact and thin-gate oxide regions. After thin-gate oxide is grown, in technologies using ion-implanted depletion- mode devices, the third mask ("X" level) defines the regions for ion-implantation. Following ion-implantation, the fourth mask opens the contact windows ("C" level). Finally, the metal is deposited over the whole wafer, and the "D" level mask defines the interconnections.

The degree of alignment of one mask to the other on the wafer is of importance if the desired geometry and hence performance objectives are to be achieved.

It is desirable to develop methods of determining accurate alignment values for all levels of alignment on a larger sample and to perform electrical measurements together with other key FET parameters which are routinely measured on the kerf.

Special MOSFET designs are disclosed which can electrically determine the degree of alignment for the various mask levels described above. The following description uses notation "A" level for the diffusion mask, "B" level for gate or thin oxide mask, "X" level for the ion-implantation mask, "C" level for the contact mask, and "D" level for the metal interconnection mask.

B-A Alignment Structure.

This structure is illustrated in Fig. 1. At each of the corners of the large diffusion 1, two MOSFETs 2 and 3 are present with common gate 4 and drain 5. The large diffusion 1 acts as a source for the first FET 2 while the smaller adjacent diffusion 6 serves as the source for the second FET 3. The gate widths of the devices are, therefore, defined by the split source diffusions 1 and 6, since the metal generously covers the thin oxide region 7. The alignment is then gaged by the amount of gate 4 developed over one of the two diffusions 1 or 6.

Consider now devices Q1, Q2 which have identical artwork width. Assuming that the B-A misalignment is Delta WB-Ay in the direction of the arrows marked Y-misalignment, the width of device 2 of Q1 is increased by Delta WB-Ay while that of device 2 of 72 is correspondingly decreased by the same amount. Since the devices are close to each other and undergo the same processing steps, it is

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