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Semi Parallel Generation of CRC Character

IP.com Disclosure Number: IPCOM000087619D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Clough, JW: AUTHOR [+3]

Abstract

A cyclic redundancy code (CRC) character is generated from a four-bit wide data bus. Generation of the CRC character from a parallel bit stream eliminates the need to convert to a serial bit stream. For equivalent data transfer rates, circuitry having one fourth the speed required for serial CRC generation can be used. Alternatively, by generating the CRC character from a parallel, rather than a serial, bit stream, it is possible to use the same type of circuit components as are used for serial CRC character generation, and operate at higher data transfer rates.

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Semi Parallel Generation of CRC Character

A cyclic redundancy code (CRC) character is generated from a four-bit wide data bus. Generation of the CRC character from a parallel bit stream eliminates the need to convert to a serial bit stream. For equivalent data transfer rates, circuitry having one fourth the speed required for serial CRC generation can be used. Alternatively, by generating the CRC character from a parallel, rather than a serial, bit stream, it is possible to use the same type of circuit components as are used for serial CRC character generation, and operate at higher data transfer rates.

The CRC character is a statistically unique character resulting from a division operation where a hardware-represented polynomial (X/16/+ X/12/+ X/5/+ 1) is the divisor and the data bits form the dividend.

As seen in the drawing, data bits 0-3 are applied to exclusive OR circuits 10- 13, respectively, which also receive bits X16-X13, respectively. The outputs of exclusive OR circuits 10-13 are applied to second and third sets of exclusive OR circuits 14-17 and 18-21, respectively. Exclusive OR circuits 14-17 also receive bits X5-X2, respectively, and exclusive OR circuits 18-21 receive bits X12-X9, respectively. With this arrangement the propagation delay is through only two stages of exclusive OR circuits. The outputs of the groups of exclusive OR circuits 10-13, 14-17 and 18-21 are applied to the data inputs of groups of flip- flops 22-25, 26-29 and 30-33, respe...