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Browse Prior Art Database

Error Transmission Across Partially Failing Interfaces

IP.com Disclosure Number: IPCOM000087637D
Original Publication Date: 1977-Feb-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Burgess, RH: AUTHOR [+4]

Abstract

A method for collecting error information about devices 7,8,9,10 normally attached to a multidropped parallel interface of the TAG IN/ OUT 3,13, BUS IN/OUT 5,11 type. The method secures the information for transmission to the interface controller 1 in spite of the fact that the normal interface protocol may be partially disabled. The method comprises the steps of detecting anomalies in the tag or bus transfers across the interface. In this regard, each controlled device 7,9 includes a functional hardware portion 8,10 and an error detector 23-29. The error detector is driven by control 17 and clock elements 19,21 indicative of TAG/OUT and BUS/OUT activity. Elements 23,25,27,29 register the anomalies.

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Error Transmission Across Partially Failing Interfaces

A method for collecting error information about devices 7,8,9,10 normally attached to a multidropped parallel interface of the TAG IN/ OUT 3,13, BUS IN/OUT 5,11 type. The method secures the information for transmission to the interface controller 1 in spite of the fact that the normal interface protocol may be partially disabled. The method comprises the steps of detecting anomalies in the tag or bus transfers across the interface. In this regard, each controlled device 7,9 includes a functional hardware portion 8,10 and an error detector 23-29. The error detector is driven by control 17 and clock elements 19,21 indicative of TAG/OUT and BUS/OUT activity. Elements 23,25,27,29 register the anomalies.

The second method step is that of communicating a first signal indicative of the occurrence of anomalies among the devices to the controller. This is instrumented by impressing a voltage along a separate multidropped path 37,38,15, called an "alert line", from the corresponding detector.

The last step is that of enabling each attached device by a second signal from the controller over selected TAG/OUT conductors 17,18 to send indicia of the detected anomalies to the controller over a corresponding dedicated conductor 31,35,41,45 in the BUS/IN portion of the interface using clocks decoded from BUS OUT by clock elements 19, 20, 21, 22.

Note, the BUS/IN path 11 consists of N parallel conductors to which the output (a...