Browse Prior Art Database

Common I O Storage Interface

IP.com Disclosure Number: IPCOM000087668D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 5 page(s) / 182K

Publishing Venue

IBM

Related People

Tutt, WE: AUTHOR

Abstract

A data processing system incorporates a common input/output (I/O) storage interface for synchronous or asynchronous operation which enables I/O devices and storage to operate with a minimum set of interface connections and permits synchronous storage to share an asynchronous I/O channel.

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Common I O Storage Interface

A data processing system incorporates a common input/output (I/O) storage interface for synchronous or asynchronous operation which enables I/O devices and storage to operate with a minimum set of interface connections and permits synchronous storage to share an asynchronous I/O channel.

In Fig. 1, processor 1 is a general purpose computer having an associated channel 2 functioning as a common interface. A representative processor, i.e., central processing unit (CPU) is microprogram-controlled by routines stored in a read-only storage (ROS). An optional console 3 may be provided in the system. As illustrated, a common bus 5 serves to connect synchronous storage 6, asynchronous storage 7 and a number of I/O attachments 9 and 10 having associated I/O devices 11 and 12, respectively. Typically, a basic interface is asynchronous and links the CPU 1 with its external resources.

In the system depicted, bus 5 is actually two bidirectional busses designated address/control and data. The interface has parallel presentation of 16 interrupt levels and cycle steal with burst-mode capabilities. Functions of the interface resolve into those initiated by the CPU 1 and those initiated by external resources with basic contention and control by CPU 1. The first category involves immediate transfers with the I/O device resource such as devices 11 and 12 or storage to or from the CPU. This is referred to as Direct Program Control (DPC). DPC operations may or may not terminate with an interrupt period. The second category of functions involves transfers from the I/O device resources directly to storage.

In a system of this nature the interface may actually comprise a multiplicity of lines as follows: ADDRESS BUS <-----> 17 DATA BUS <-----> 18 ADDRESS
GATE ------) 1 ADDRESS GATE RETURN <------ 1 DATA STROBE ------> 1
REQUEST IN BUS <------ 17 POLL IDENTIFIER ------> 5 POLL ------) 1 POLL
PRIME ------) 1 POLL PROPAGATE ------) 1 POLL RETURN <------ 1 BURST
RETURN <------ 1 SERVICE GATE ------> 1 SERVICE GATE RETURN <------ 1
OUTPUT/INPUT INDICATOR <-----) 1 WORD/BYTE INDICATOR <-----> 1
CYCLE STEAL STATUS BUS ------) 4 HALT, MACHINE CHECK RESET ------> 1
CONDITION CODE IN <------ 3 SYSTEM RESET ------> INITIATE INITIAL
PROGRAM LOAD ------) 1 INITIAL PROGRAM LOAD (IPL) <------ 1 POWER ON
RESET ------> STORAGE GATE A ------) 1 STORAGE GATE B ------...