Browse Prior Art Database

Timer External Clock and Gate

IP.com Disclosure Number: IPCOM000087669D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Bourke, DG: AUTHOR [+2]

Abstract

The flexibility of a timer is increased by providing for capability of use as a pulse counter, pulse duration counter, or pulse averager under program control, as directed, in a data processing system.

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Timer External Clock and Gate

The flexibility of a timer is increased by providing for capability of use as a pulse counter, pulse duration counter, or pulse averager under program control, as directed, in a data processing system.

The advantages are described in conjunction with a timer attachment to a central processing unit (CPU). The attachment would present a logical interface to a controlling program. Timer External Clock and Gate signals are provided by a user of the basic timer as a pulse counter or pulse duration counter.

In Fig. 1, a clock selector circuit 1, under control of the program lines 2, provides for selection of a number of Internal Clocks (IC1, IC2,--ICn) 3 (usually provided with timers) and an additional External Clock (EC) input on line 4. Also, a selector network 6 is provided under program control for enabling or disabling an External Gate (EG) on line 7 under the envelope of the program running of the timers.

Normally, an Internal Clock is selected and the External Gate is disabled when timer 10 is caused to run by the program. Timer 10 will generate carries whenever it overflows, causing an interrupt to the program. The program uses these interrupts via circuit 11 to keep track of time intervals, time of day, etc. The normal operation is illustrated in Fig. 2. The first interrupt would be generated as a function of the time interval of the Interval Clock (TC) and the initial value IV loaded into timer 10 by the program prior to the running of the timer. The timer would then continue to interrupt periodically as a function of TC and its maximum counting modules 2 EXP N, where N equals the number of stages in the counter.

Operation as a "pulse counter" involves selecting the External Clock signal on line 4 while keeping the External Gate on line 7 disabled (Fig. 3). When caused to run, timer 10 then accumulates pulses from an external device. It interrupts the first time when it h...