Browse Prior Art Database

Nonvolatile Memory Structure

IP.com Disclosure Number: IPCOM000087687D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Howard, LF: AUTHOR

Abstract

These variable threshold nonvolatile memory cells provide a programmable read-only memory capable of being fabricated by processes developed for fixed threshold dual dielectric devices.

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Nonvolatile Memory Structure

These variable threshold nonvolatile memory cells provide a programmable read-only memory capable of being fabricated by processes developed for fixed threshold dual dielectric devices.

Figs. 1 and 2 show a portion of an array of variable threshold memory cells each of which includes a bit line and a high potential line VH diffused into a semiconductor substrate 10. Overlying the surface of substrate 10 is a dielectric layer 12 which includes a thin gate area located between each pair of bit and VH lines. The gate region comprises a dual dielectric structure, preferably silicon nitride over silicon dioxide having a composite thickness of 400-1000 angstrom units in thickness. The ratio of oxide to nitride thickness is chosen to provide stable fixed threshold field-effect transistor (FET) characteristics, rather than requiring a thin tunneling oxide layer as do most variable threshold dual dielectric structures. Orthogonal to the diffusions are a plurality of word lines which provide accessing of the memory cells.

To program the memory cells, the word and bit lines of a selected cell are biased so as to provide hot electron injection, in the case of n-channel devices, from the substrate into the dual dielectric. Negative charge trapped in the nitride and at the interface between the oxide and nitride layers provides an increase in threshold voltage in devices so selected. In order to provide a sufficient quantity of hot carriers, a train of pulses is applied to the bit line diffusion having a period of about 1.0 microsecond with a low level of about one volt below the substrate potential, in order to forward bias the bit line to substrate junction, and a high level of about 9 volts above the substrate potential. The forward and reverse biases may be applied for approximately equal portions of the period. In devices to be written, the selected word line is held at about 16 volts in order to provide a suff...