Browse Prior Art Database

Quick Fix Engineering Change Mechanism for LSI Chips

IP.com Disclosure Number: IPCOM000087709D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Howe, LD: AUTHOR [+2]

Abstract

A mechanism is described for enabling quick-fix engineering changes to be made to the circuitry on large-scale integration (LSI) chips located in data processing or other electronic equipment. This quick-fix capability is obtained by using scan ring latches to enable a dynamic segregation of different portions of the circuitry on each LSI chip and by incorporating one or more unit logic chips into the LSI hardware.

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Quick Fix Engineering Change Mechanism for LSI Chips

A mechanism is described for enabling quick-fix engineering changes to be made to the circuitry on large-scale integration (LSI) chips located in data processing or other electronic equipment. This quick-fix capability is obtained by using scan ring latches to enable a dynamic segregation of different portions of the circuitry on each LSI chip and by incorporating one or more unit logic chips into the LSI hardware.

In future digital computers and data processors, for example, most of the electronic circuitry will be embedded in very small LSI chips. Each LSI chip will include several hundred electronic circuits and each computer will include hundreds of such LSI chips. Because of the very considerable complexity of the circuitry and the inability to anticipate all possible uses of the computer, it will sometimes happen that a logic design defect or "bug" will not be discovered until after the computer has been installed and put into use at the customer's place of business. The problem then becomes one of how to fix the defect very quickly so that the customer does not lose the use of his computer for any appreciable length of time.

Unffortuately, the wiring patterns and semiconductor devices embedded in the LSI chip are microscopic in size and are generally inaccessible for repair purposes. The ultimate solution is to design a new chip and to substitute it for the chip having the defective logic. Unfortunately, the total turnaround time required to do this is on the order of one or two months or more. The chip must be redesigned, the new design must be tested by simulation, any errors in the redesign must be corrected, the new chip must be manufactured and the manufactured chip must be tested. All of this takes much too long for the unhappy customer with the idle computer.

The mechanism described herein enables LSI chip logic defects to be corrected in a matter of hours or a few days at most. This mechanism enables the logic defect to be circumvented without having to await the arrival of a redesigned chip.

Fig. 1 illustrates in a simplified manner a more or less typical application of this quick-fix mechanism. In particular, a number of LSI chips 10-14, each designated "CLC" for "combinational logic chip," are mounted on a chip carrier 15 which may take the form of either a printed-circuit card or an integrated circuit (IC) substrate. The LSI chips 10-14 are interconnected by means of printed- circuit wiring 16 formed on the carrier 15, with some of this wiring 16 also being connected to input/ output pins 17 for the carrier 15. Each of the CLC chips 10- 14 contains the usual kind of combinational logic circuitry, registers, latches and the like, normally associated with digital computers and data processors.

Also incorporated on the chip carrier 15 is a unit logic chip (ULC) 18. This unit logic chip 18 is an LSI chip having formed thereon a collection of disconnected "spare pa...