Browse Prior Art Database

LSI Chip Mechanism for Enabling Quick Fix Engineering

IP.com Disclosure Number: IPCOM000087710D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Kriger, RJ: AUTHOR

Abstract

A mechanism is described for enabling quick-fix or temporary-fix engineering changes to be made to the circuitry on large-scale integration (LSI) chips located in data processing or other electronic equipment. This quick-fix capability is obtained by proper partitioning or segregation of the circuitry on each LSI chip and by incorporating one or more unit logic chips into the LSI hardware.

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LSI Chip Mechanism for Enabling Quick Fix Engineering

A mechanism is described for enabling quick-fix or temporary-fix engineering changes to be made to the circuitry on large-scale integration (LSI) chips located in data processing or other electronic equipment. This quick-fix capability is obtained by proper partitioning or segregation of the circuitry on each LSI chip and by incorporating one or more unit logic chips into the LSI hardware.

Fig. 1 illustrates in a simplified manner a more or less typical application of the quick-fix mechanism. A general discussion of this subject and a specific description of Fig. 1 are found on pages 3719-3722 of this issue.

Fig. 2 illustrates the partitioning aspect of the quick-fix mechanism with relation to the combinational logic chip (CLC) 11. As shown, the circuits on each chip are grouped into zones and the circuits in any given zone are not connected to the circuits in any of the other zones. The circuitry in each zone has its own separate sets of chip input pins and chip output pins. This same partitioning concept is applied to each of the other CLC chips 10 and 12-14.

Fig. 3 shows the implementation of the quick-fix technique for an assumed case of a logic defect in the zone 3 circuitry on chip 11.

In this case, the chip carrier wiring running to the input and output pins of zone 3 of chip 11 are broken or severed as indicated by the X marks 20. The input and output pins of the unit logic chip (ULC) 18 are then interconnected by means of discrete wiring 21 so as to enable the circuits on the ULC chip 18 to perform the correct logical functions for zone 3 of chip 11. The ULC chip 18 is then connected by way of further discrete wiring 22 to the existing wiring 16 so as to enable the ULC chip 18 to take the place of the zone 3 circuitry of chip 11. The discrete wiring 21 and 22 is formed on the surface of the chip carrier 15 by proper application of conductive material thereto.

By way of example, each CLC chip 10-14 may...