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High Current Internal Contact Structure for Integrated Circuits

IP.com Disclosure Number: IPCOM000087717D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Benjamin, CE: AUTHOR

Abstract

Metal studs 3 are first formed over the individual contact holes in the thermal silicon dioxide layer 4 on silicon wafer 5 and embedded in a polyimide matrix 6. Except in "self-aligned" processes where a single photoresist step is used to define both contact holes and studs, an overlap will be required, as shown in the drawing, to assure complete contact coverage with normal registration tolerances. This results in a nonplanar stud surface, as shown.

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High Current Internal Contact Structure for Integrated Circuits

Metal studs 3 are first formed over the individual contact holes in the thermal silicon dioxide layer 4 on silicon wafer 5 and embedded in a polyimide matrix 6. Except in "self-aligned" processes where a single photoresist step is used to define both contact holes and studs, an overlap will be required, as shown in the drawing, to assure complete contact coverage with normal registration tolerances. This results in a nonplanar stud surface, as shown.

The first level lands 7 are subsequently formed by repeating this process, using different lithography processes. These lands are also embedded in a polyimide matrix 8. Layer thicknesses for studs and horizontal lands do not necessarily have to be the same. Any step in the stud surface will be replicated in the top of the land because of the directionality of the evaporation process.

Additional metallurgy/insulator levels can be built up by repeating these processes with appropriate photo or E-beam lithography patterns Very high resolutions are achievable with this system. Unlike the evaporated metal, the polyimide effectively planarizes over small recesses, such as those described above, resulting in a fully planarized multilevel structure with no horizontal design restrictions.

With this system, contact holes can be formed with vertical walls, for example, by reactive ion etching, and corresponding closer spacing. Device land capacitances can also be r...