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Semiconductor Chip Interface Circuit

IP.com Disclosure Number: IPCOM000087723D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Nijhuis, R: AUTHOR [+4]

Abstract

This is a layout of a circuit for receiving and driving signals between ground-down and ground-up logic chips.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

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Semiconductor Chip Interface Circuit

This is a layout of a circuit for receiving and driving signals between ground- down and ground-up logic chips.

The chip is typically a logic masterslice containing internal logic cells, off-chip drivers and off-chip receivers. A single layout type is wired to be either a receiver or a driver, thereby saving space on the chip, particularly where more drivers than receivers are required, or vice-versa.

Fig. 1 illustrates a layout where the single transistor is formed adjacent a bed of three resistors. The collector, emitter, base and Schottky barrier diode regions of the transistor are identified as 4, 3, 2 and D1, respectively. A ground connection is supplied by the ground bus and the positive potential is supplied by second-level metallization (not shown).

Fig. 2 shows the receiver. The connections among the components are made by means of first-level metal wiring (not illustrated). For example, a first- level metal connection is made between the output resistor R3 and the emitter of the transistor. The input connection is made at the upper contact of resistor R1. Resistor R4 and potential-V are located elsewhere on the chip.

Fig. 3 illustrates the driver circuit which uses the same transistor, diode D1 and resistor R1, with the output taken from collector 4. The main difference between the circuits lies in the wiring pattern of the first-level metallization.

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