Browse Prior Art Database

Universal Latch

IP.com Disclosure Number: IPCOM000087724D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Montegari, FA: AUTHOR

Abstract

The universal latch circuit depicted in Fig. 1 is a T/2/L AND-INVERT with the collector of T3 connected to the base of T2 to form a feedback path. T3 is latched OFF if node A is pulsed down, while B is held down. The latch is reset by pulsing node B up, while A is held up.

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Universal Latch

The universal latch circuit depicted in Fig. 1 is a T/2/L AND-INVERT with the collector of T3 connected to the base of T2 to form a feedback path. T3 is latched OFF if node A is pulsed down, while B is held down. The latch is reset by pulsing node B up, while A is held up.

Figs. 2 through 4 depict variations of the universal latch to provide logical set and reset functions. An off-chip set input may be added to the latch of Fig. 4 by connecting one of the set input transistors T2 as an off-chip receive diode to accept levels from an emitter follower.

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