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Memory Cell Power Up Circuit

IP.com Disclosure Number: IPCOM000087729D
Original Publication Date: 1977-Mar-01
Included in the Prior Art Database: 2005-Mar-03
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Denis, B: AUTHOR [+3]

Abstract

This circuit makes it possible to increase the current in the load transistors of a memory cell when the cell is restored, the current supplied to the cell having to remain low during both standby and selection cycles.

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Memory Cell Power Up Circuit

This circuit makes it possible to increase the current in the load transistors of a memory cell when the cell is restored, the current supplied to the cell having to remain low during both standby and selection cycles.

In the standby mode, word lines WL1 and WL2 of cells C1 and C2 assume a high level. Input transistors T1 and T2 transmit this high level to node A which drives the base of transistor T3, thereby turning it on. The voltage level applied to node B, which drives the base of transistor T4, is low and the DC voltage VR applied to node C, which drives the base of transistor T5, assumes an intermediate level. Transistor T5 of the current switch, formed of T3, T4 and T5, is off since T3 is on. Then, transistor T6 is on, keeping transistor T7 off. A low standby current is then supplied by resistor R7.

When a word line is selected, its level is low and node A assumes a low level, cutting off transistor T3. The base of transistor T4 is raised (node B) so that the latter is on and transistor T5 remains off. Transistor T7 is off and a low current is supplied to the cells by resistor R7.

Now, upon termination of the selection mode, the cells must receive a high current for the regeneration cycle. The level at node B is lowered and transistor T4 is turned off. The base of transistor T3 is maintained at a low level by the word line which, though unselected, rises very slowly through the standby current and the capacitive effect of the...